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fujitsu microelectronics data sheet copyright?2002-2008 fujitsu microelec tronics limited all rights reserved 2008.8 the information for microcontroller suppor ts is shown in the following homepage. be sure to refer to the "check sheet" for the latest cautions on development. "check sheet" is seen at the following support page "check sheet" lists the minimal requirement items to be checked to prevent problems beforehand in system development. http://edevice.fujitsu.com/micom/en-support/ 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90435 series mb90437l (s) /438l (s) /f438l (s) mb90439 (s) /f439 (s) /v540g description the mb90435 series with flash rom is spec ially designed for industrial applications. the instruction set by f 2 mc-16lx cpu core inherits an at architecture of the f 2 mc* family with additional instruction sets for high-level languages, extended ad dressing mode, enhanced multiplication/division instruc- tions, and enhanced bit manipulation instructions.the micr o controller has a 32-bit accumulator for processing long word data. the mb90435 series has peripheral resources of 8/10-bit a/d converters, uart (sci) , extended i/o serial interfaces, 8/16-bit timer, i/o timer (input capture (icu) , output compare (ocu) ) . * : f 2 mc is the abbreviation of fujitsu flexible microcontroller. features ?clock embedded pll clock multiplication circuit operating clock (pll clock) can be selected from : divided-by -2 of oscillation or one to four times the oscillation minimum instruction execution time : 62.5 ns (operation at oscillation of 4 mhz, four times the oscillation clock, v cc of 5.0 v) subsystem clock : 32 khz (continued) ds07-13727-2e
mb90435 series 2 ds07-13727-2e instruction set to optimize controller applications rich data types (bit, byte, word, long word) rich addressing mode (23 types) enhanced signed multiplication/division inst ruction and reti instruction functions enhanced precision calculation rea lized by the 32-bit accumulator instruction set designed for high level l anguage (c language) and multi-task operations adoption of system stack pointer enhanced pointer indirect instructions barrel shift instructions program patch function (for two address pointers) enhanced execution speed : 4-byte instruction queue enhanced interrupt function : 8 levels, 34 factors automatic data transmission func tion independent of cpu operation extended intelligent i/o service function (ei 2 os) embedded rom size and types mask rom : 64 kbytes / 128 kbytes / 256 kbytes flash rom : 128 kbytes/256 kbytes embedded ram size : 2 kbytes/4 kbytes/6 kbytes/8 kbytes (evaluation chip) flash rom supports automatic programming, embedded algorithm write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm hard-wired reset vector available in order to point to a fixed boot sector in flash memory erase can be performed on each block block protection with external programming voltage low-power consumption (stand-by) mode sleep mode (mode in which cpu operating clock is stopped) stop mode (mode in which oscillation is stopped) cpu intermittent operation mode clock mode hardware stand-by mode process 0.5 m cmos technology i/o port general-purpose i/o ports : 81 ports timer watchdog timer : 1 channel 8/16-bit ppg timer : 8/16-bit 4 channels 16-bit re-load timer : 2 channels 16-bit i/o timer 16-bit free-run timer : 1 channel input capture : 8 channels output compare : 4 channels extended i/o serial interface : 1 channel uart 0 with full-duplex double buffer (8-bit length) clock asynchronized or clock synchronized (with st art/stop bit) transmission can be selectively used. (continued)
mb90435 series ds07-13727-2e 3 (continued) uart 1 with full-duplex double buffer (8-bit length) clock asynchronized or clock synchroniz ed serial (extended i/o serial) can be used. external interrupt circuit (8 channels) a module for starting an extended intelligent i/o service (ei 2 os) and generating an external interrupt which is triggered by an external input. delayed interrupt generation module generates an interrupt re quest for switching tasks. 8/10-bit a/d converter (8 channels) 8/10-bit resolution can be selectively used. starting by an external trigger input. conversion time : 26.3 s external bus interface : maximum address space 16 mbytes package: qfp-100, lqfp-100
mb90435 series 4 ds07-13727-2e product lineup (continued) features mb90f438l (s) /f439 (s) mb90437l (s) /438l (s) /439 (s) mb90v540g cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier ( 1, 2, 3, 4, 1/2 when pll stop) minimum instruction exection time : 62.5 ns (4 mhz osc. pll 4) rom flash memory mb90f438l(s) : 128 kbytes mb90f439(s) : 256 kbytes mask rom : mb90437l(s): 64 kbytes mb90438l(s): 128 kbytes mb90439(s): 256 kbytes external ram mb90f438l(s) : 4 kbytes mb90f439(s) : 6 kbytes mb90437l(s): 2 kbytes mb90438l(s): 4 kbytes mb90439(s): 6 kbytes 8 kbytes clocks mb90f438l/f439 : two clocks system mb90f438ls/f439s : one clock system mb90437l/438l/439 : two clocks system mb90437ls/438ls/439s : one clock system two clocks system* 1 operating voltage range *3 temperature range ? 40 c to 105 c package qfp100, lqfp100 pga-256 emulator-specify power supply *2 ? none uart0 full duplex double buffer support asynchronous/synchronous (with start/stop bit) transfer baud rate : 4808/5208/9615/10417/19230/ 38460/62500/500000 bps (asynchronous) 500 k/1 m/2 mbps (synchronous) at system clock = 16 mhz uart1 (sci) full duplex double buffer asynchronous (start-stop synchronized) and clk-synchronous communication baud rate : 1202/2404/4808/9615/19230/ 31250/38460/62500 bps (asynchronous) 62.5 k/125 k/250 k/500 k/1 m/2 mbps (syn chronous) at 6, 8, 10, 12, 16 mhz serial i/o transfer can be started from msb or lsb supports internal clock synchronized transf er and external clock synchronized transfer supports positive-edge and nagative-edge clock synchronization baud rate : 31.25 k/62.5 k/125 k/500 k/1 mbps at system clock = 16 mhz a/d converter 10-bit or 8-bit resolution 8 input channels conversion time : 26.3 s (per one channel)
mb90435 series ds07-13727-2e 5 (continued) *1 : if the one clock system is used, equip x0 a and x1a with clocks from the tool side. *2 : it is setting of dip switch s2 when emulator pod (m b2145-507) is used.please refe r to the mb2145-507 hardware manual (2.7 emulator-specific power pin) about details. *3 : operating voltage range features mb90f438l (s) /f439 (s) mb90437l (s) /438l (s) /439 (s) mb90v540g 16-bit reload timer (2 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys = system clock frequency) supports external event count function signals an interrupt when overflow 16-bit free-run timer supports timer clear when a match with output compare (channel 0) operation clock freq. : fsys/2 2 , fsys/2 4 , fsys/2 6 , fsys/2 8 (fsys = system clock freq.) 16-bit output compare (4 channels) signals an interrupt when a match with 16-bit free-run timer four 16-bit compare registers a pair of compare registers can be used to generate an output signal 16-bit input capture (8 channels) rising edge, falling edge or ri sing & falling edge sensitive four 16-bit capture registers signals an interrupt upon external event 8/16-bit programmable pulse generator (4 channels) supports 8-bit and 16-bit operation modes eight 8-bit reload counters eight 8-bit reload registers for l pulse width eight 8-bit reload registers for h pulse width a pair of 8-bit reload counters can be configur ed as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 4 output pins operation clock freq. : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 s@fosc = 4 mhz (fsys = system clock frequency, fosc = oscillation clock frequency) 32 khz sub-clock sub-clock for low power operation external interrupt (8 channels) can be programmed edge sensit ive or level sensitive external bus interface external access using the select able 8-bit or 16-bit bus is enabled (external bus mode.) i/o ports virtually all external pins can be used as general purpose i/o all push-pull outputs and schmitt trigger inputs bit-wise programmable as input/output or peripheral signal flash memory supports automatic programming, embeded algorithm write/erase/erase-suspend/erase-resume commands a flag indicating completion of the algorithm number of erase cycles : 10,000 times data retention time : 10 years boot block configuration erase can be performed on each block block protection by externally programmed voltage products operation guarantee range mb90f439 (s) /439 (s) /v540g 4.5 v to 5.5 v mb90f438l (s) /437l (s) /438l (s) 3.5 v to 5.5 v
mb90435 series 6 ds07-13727-2e pin assignment (continued) (top view) (fpt-100p-m06) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 x0a x1a pa0 rst p97 p96 p95 p94 p93/int3 p92/int2 p91/int1 p90/int0 p87/tot1 p86/tin1 p85/out1 p84/out0 p83/ppg3 p82/ppg2 p81/ppg1 p80/ppg0 p77/out3/in7 p76/out2/in6 p75/in5 p74/in4 p73/in3 p72/in2 p71/in1 p70/in0 hst md2 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p20/a16 p21/a17 p22/a18 p23/a19 p24/a20 p25/a21 p26/a22 p27/a23 p30/ale p31/rd v ss p32/wrl/wr p33/wrh p34/hrq p35/hak p36/rdy p37/clk p40/sot0 p41/sck0 p42/sin0 p43/sin1 p44/sck1 v cc p45/sot1 p46/sot2 p47/sck2 c p50/sin2 p51/int4 p52/int5 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 p53/int6 p54/int7 p55/adtg av cc avrh avrl av ss p60/an0 p61/an1 p62/an2 p63/an3 v ss p64/an4 p65/an5 p66/an6 p67/an7 p56/tin0 p57/tot0 md0 md1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p10/ad08 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v cc x1 x0 v ss
mb90435 series ds07-13727-2e 7 (continued) (top view) (fpt-100p-m20) p22/a18 p23/a19 p24/a20 p25/a21 p26/a22 p27/a23 p30/ale p31/rd v ss p32/wrl/wr p34/hrq p33/wrh p35/hak p36/rdy p37/clk p40/sot0 p41/sck0 p42/sin0 p43/sin1 p44/sck1 v cc p45/sot1 p46/sot2 p47/sck2 c 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 rst p97 p96 p95 p94 p93/int3 p92/int2 p91/int1 p90/int0 p87/tot1 p86/tin1 p85/out1 p84/out0 p83/ppg3 p82/ppg2 p81/ppg1 p80/ppg0 p77/out3/in7 p76/out2/in6 p75/in5 p74/in4 p73/in3 p72/in2 p71/in1 p70/in0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 p21/a17 p20/a16 p17/ad15 p16/ad14 p15/ad13 p14/ad12 p13/ad11 p12/ad10 p11/ad09 p10/ad08 p07/ad07 p06/ad06 p05/ad05 p04/ad04 p03/ad03 p02/ad02 p01/ad01 p00/ad00 v cc x1 x0 v ss x0a x1a pa0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p50/sin2 p51/int4 p52/int5 p53/int6 p54/int7 p55/adtg av cc avrh avrl av ss p60/an0 p61/an1 p62/an2 p63/an3 v ss p64/an4 p65/an5 p66/an6 p67/an7 p56/tin0 p57/tot0 md0 md1 md2 hst
mb90435 series 8 ds07-13727-2e pin description (continued) pin no. pin name circuit type function lqfp *2 qfp *1 80 81 82 83 x0 x1 a (oscillation) high speed crystal oscillator input pins 78 80 x0a a (oscillation) low speed crystal oscillator i nput pins. for the one clock system parts, perfom external pull-down processing. 77 79 x1a low speed crystal oscillator i nput pins. for the one clock system parts, leave it open. 75 77 rst b external reset request input pin 50 52 hst c hardware standby input pin 83 to 90 85 to 92 p00 to p07 i general i/o port with programmable pull-up. this function is enabled in the single-chip mode. ad00 to ad07 i/o pins for 8 lower bits of the external address/data bus. this function is enabled when the external bus is enabled. 91 to 98 93 to 100 p10 to p17 i general i/o port with programmable pull-up. this function is enabled in the single-chip mode. ad08 to ad15 i/o pins for 8 higher bits of the external address/data bus. this function is enabled when the external bus is enabled. 99 to 6 1 to 8 p20 to p27 i general i/o port with programmable pull-up. in external bus mode, this function is valid wh en the corresponding bits in the external address output control register (hacr) are set to ?1?. a16 to a23 8-bit output pins for a16 to a23 at the external address bus. in external bus mode, this function is valid when the correspond- ing bits in the external addres s output control register (hacr) are set to ?0?. 79 p30 i general i/o port with programmable pull-up. this function is enabled in the single-chip mode. ale address latch enable output pin. this function is enabled when the external bus is enabled. 810 p31 i general i/o port with programmable pull-up. this function is enabled in the single-chip mode. rd read strobe output pin for the data bus. this function is enabled when the external bus is enabled. 10 12 p32 i general i/o port with programmable pull-up. this function is enabled in the single-chip mode or when the wr /wrl pin output is disabled. wrl write strobe output pin for th e data bus. this function is enabled when both the exte rnal bus and the wr /wrl pin output are enabled. wrl is write-strobe output pin for the lower 8 bits of the data bus in 16-bit access. wr is write-strobe output pin for the 8 bits of the data bus in 8-bit access. wr
mb90435 series ds07-13727-2e 9 (continued) pin no. pin name circuit type function lqfp *2 qfp *1 11 13 p33 i general i/o port with programmable pull-up. this function is enabled in the single-chip mode, external bus 8-bit mode or when wrh pin output is disabled. wrh write strobe output pin for the 8 higher bits of the data bus. this function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the wrh output pin is enabled. 12 14 p34 i general i/o port with programmable pull-up. this function is enabled in the single-chip mode or when the hold function is disabled. hrq hold request input pin. this function is enabled when both the external bus and the hold functions are enabled. 13 15 p35 i general i/o port with programmable pull-up. this function is enabled in the single-chip mode or when the hold function is disabled. hak hold acknowledge output pin. this function is enabled when both the external bus and th e hold functions are enabled. 14 16 p36 i general i/o port with programmable pull-up. this function is enabled in the single-chip mode or when the external ready function is disabled. rdy ready input pin. this func tion is enabled when both the external bus and the external ready functions are enabled. 15 17 p37 h general i/o port with programmable pull-up. this function is enabled in the single-chip mode or when the clk output is disabled. clk clk output pin. this func tion is enabled when both the external bus and clk outputs are enabled. 16 18 p40 g general i/o port. this function is enabled when uart0 disables the serial data output. sot0 serial data output pin for uart 0. this function is enabled when uart0 enables the serial data output. 17 19 p41 g general i/o port. this function is enabled when uart0 disables serial clock output. sck0 serial clock i/o pin for uart0. this function is enabled when uart0 enables the serial clock output. 18 20 p42 g general i/o port. this function is always enabled. sin0 serial data input pin for uart 0. set the corre sponding port direction register to input if this function is used. 19 21 p43 g general i/o port. this function is always enabled. sin1 serial data input pin for uart 1. set the corre sponding port direction register to input if this function is used.
mb90435 series 10 ds07-13727-2e (continued) pin no. pin name circuit type function lqfp *2 qfp *1 20 22 p44 g general i/o port. this function is enabled when uart1 disables the clock output. sck1 serial clock pulse i/o pin fo r uart1. this function is enabled when uart1 enables the serial clock output. 22 24 p45 g general i/o port. this function is enabled when uart1 disables the serial data output. sot1 serial data output pin for uart 1. this function is enabled when uart1 enables the serial data output. 23 25 p46 g general i/o port. this function is enabled when the extended i/o serial interface disables the serial data output. sot2 serial data output pin for the extended i/o serial interface. this function is enabled when the extended i/o serial interface enables the serial data output. 24 26 p47 g general i/o port. this function is enabled when the extended i/o serial interface disables the clock output. sck2 serial clock pulse i/o pin for the extended i/o serial interface . this function is enabled when the extended i/o serial interface enables the serial clock output. 26 28 p50 d general i/o port. this function is always enabled. sin2 serial data input pin for the extended i/o serial interface . set the corresponding port direction register to input if this function is used. 27 to 30 29 to 32 p51 to p54 d general i/o port. this function is always enabled. int4 to int7 external interrupt request input pins for int4 to int7. set the corresponding port direction register to input if this function is used. 31 33 p55 d general i/o port. this function is always enabled. adtg trigger input pin for the a/d c onverter. set the corresponding port direction register to i nput if this function is used. 36 to 39 38 to 41 p60 to p63 e general i/o port. this function is enabled when the analog input enable register specifies a port. an0 to an3 analog input pins for the 8/10-bit a/d converter. this function is enabled when the analog input enable register specifies a/d. 41 to 44 43 to 46 p64 to p67 e general i/o port. the function is enabled when the analog input enable register specifies a port. an4 to an7 analog input pins for the 8/10-bit a/d converter. this function is enabled when the analog input enable register specifies a/d. 45 47 p56 d general i/o port. this function is always enabled. tin0 event input pin for the 16-bit reload timers 0. set the corresponding port direction register to input if this function is used.
mb90435 series ds07-13727-2e 11 (continued) pin no. pin name circuit type function lqfp *2 qfp *1 46 48 p57 d general i/o port. this functi on is enabled when the 16-bit reload timers 0 disables the output. tot0 output pin for the 16-bit reload timers 0. this function is enabled when the 16-bit reload timers 0 enables the output. 51 to 56 53 to 58 p70 to p75 d general i/o ports. this fu nction is always enabled. in0 to in5 trigger input pins for input captures icu0 to icu5. set the corresponding port direction register to input if this function is used. 57 , 58 59 , 60 p76 , p77 d general i/o ports. this functi on is enabled when the ocu disables the waveform output. out2 , out3 event output pins for output compares ocu2 and ocu3. this function is enabled when the ocu enables the waveform output. in6 , in7 trigger input pins for input c aptures icu6 and icu7. set the corresponding port direction regi ster to input and disable the ocu waveform output if this function is used. 59 , 62 61 to 64 p80 to p83 d general i/o ports. this function is enabled when 8/16-bit ppg disables the waveform output. ppg0 to ppg3 output pins for 8/16-bit ppgs. this function is enabled when 8/16-bit ppg enables the waveform output. 63 , 64 65 , 66 p84 , p85 d general i/o ports. this functi on is enabled when the ocu disables the waveform output. out0 , out1 waveform output pins for output compares ocu0 and ocu1. this function is enabled when the ocu enables the waveform output. 65 67 p86 d general i/o port. this function is always enabled. tin1 input pin for the 16-bit re load timers 1. set the corresponding port direction register to input if this function is used. 66 68 p87 d general i/o port. this functi on is enabled when the 16-bit reload timers 0 disables the output. tot1 output pin for the 16-bit reload timers 1.this function is enabled when the 16-bit reload timers 1 enables the output. 67 to 70 69 to 72 p90 to p93 d general i/o port. this function is always enabled. int0 to int3 external interrupt request input pins for int0 to int3. set the corresponding port direction register to input if this function is used. 71 73 p94 d general i/o port.
mb90435 series 12 ds07-13727-2e (continued) *1 : fpt-100p-m06 *2 : fpt-100p-m20 pin no. pin name circuit type function lqfp *2 qfp *1 72 74 p95 d general i/o port. 73 75 p96 d general i/o port. 74 76 p97 d general i/o port. 76 78 pa0 d general i/o port. 32 34 av cc power supply power supply pin for the a/d co nverter. this power supply must be turned on or off while a voltage higher than or equal to av cc is applied to v cc . 35 37 av ss power supply power supply pin for the a/d converter. 33 35 avrh power supply external reference voltage input pin for the a/d converter. this power supply must be tur ned on or off while a voltage higher than or equal to avrh is applied to av cc . 34 36 avrl power supply external reference voltage input pin for the a/d converter. 47 48 49 50 md0 md1 c input pins for specifying the op erating mode. the pins must be directly connected to v cc or v ss . 49 51 md2 f input pin for specifying the ope rating mode. the pin must be directly connected to v cc or v ss . 25 27 c ? power supply stabilization capaci tor pin. it should be connect- ed externally to an 0.1 f ceramic capacitor. 21, 82 23, 84 v cc power supply input pin for power supply (5.0 v) . 9, 40, 79 11, 42, 81 v ss power supply input pin for power supply (0.0 v) .
mb90435 series ds07-13727-2e 13 i/o circuit type (continued) circuit type diagram remarks a high-speed oscillation feedback resistor : 1 m ? approx. low-speed oscillation feedback resistor : 10 m ? approx. b hysteresis input pull-up resistor : 50 k ? approx. c hysteresis input d cmos level output cmos hysteresis input x1,x1a x0,x0a hard, soft standby control clock input r r (pull-up) hys input r hys input r p-ch n-ch hys input v cc
mb90435 series 14 ds07-13727-2e (continued) circuit type diagram remarks e cmos level output cmos hysteresis input analog input f hysteresis input pull-down resistor : 50 k ? approx. (except flash devices) g cmos level output cmos hysteresis input ttl level input (flash devices in flash writer mode only) r v cc p-ch n-ch hys input analog input p-ch n-ch r r (pull-down) hys input r v cc p-ch n-ch r t hys input ttl level input
mb90435 series ds07-13727-2e 15 (continued) circuit type diagram remarks h cmos level output cmos hysteresis input programmable pull-up resistor : 50 k ? approx. i cmos level output cmos hysteresis input ttl level input (flash devices in flash writer mode only) programmable pull-up resistor : 50 k ? approx. v cc p-ch p-ch n-ch v cc hys inpu t pull-up on/off select signal r r v cc p-ch p-ch n-ch r t v cc pull-up on/off select signal hys input ttl level input
mb90435 series 16 ds07-13727-2e handling devices (1) preventing latch-up cmos ic chips may suffer latch- up under the following conditions : a voltage higher than v cc or lower than v ss is applied to an input or output pin. a voltage higher than the rate d voltage is applied between v cc and v ss . the avcc power supply is applied before the v cc voltage. latch-up may increase the power supply current dras tically, causing thermal damage to the device. for the same reason, care must also be taken in not allowing the analog power-supply voltage (av cc , avrh) to exceed the digital power-supply voltage. (2) handling unused pins leaving unused input pins open may result in misbehav ior or latch up and possib le permanent damage of the device. therefor they must be pulled up or pulled down th rough resistors. in this case those resistors should be more than 2 k ? . unused bi-directional pins should be set to the output state and can be left open, or the input state with the above described connection. (3) using external clock to use external clock, drive x0 pin only and leave x1 pin unconnected. below is a diagram of how to use external clock. (4) use of the sub-clock use one clock system parts when the sub-clock is not us ed. in that case, pull-down the pin x0a and leave the pin x1a open. when using two clock system parts, a 32 khz oscillator has to be con nected to the x0a and x1a pins. (5) power supply pins (v cc /v ss ) in products with multiple v cc or v ss pins, the pins of a same potential ar e internally connected in the device to avoid abnormal operations including la tch-up. however you must connect t he pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. make sure to connect v cc and v ss pins via the lowest impedance to power lines. it is recommended to provide a bypass capacitor of around 0.1 f between v cc and v ss pins near the device. x0 x1 mb90435 series open v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss mb90435 series
mb90435 series ds07-13727-2e 17 (6) pull-up/down resistors the mb90435 series does not support intern al pull-up/down resistors (except port0 ? port3 : pull-up resistors) . use external components where needed. (7) crystal oscillator circuit noises around x0 or x1 pins may be possible causes of abnormal operations. make sure to provide bypass capacitors via the shortest distances from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, th at lines of oscillation circuits do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board artwork surrounding x0 and x1 pins with a ground area for stabilizing the operation. (8) turning-on sequence of power supp ly to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , avrh, avrl) and analog inputs (an0 to an7) after turning-on the digital power supply (v cc ) . turn-off the digital power after turning off the a/d conv erter supply and analog inputs. in this case, make sure that the voltage does not exceed avrh or av cc (turning on/off the analog and digital power supplies simulta- neously is acceptable) . (9) connection of unused pins of a/d converter connect unused pins of a/d converter to av cc = v cc , av ss = avrh = v ss . (10) n.c. pin the n.c. (internally connecte d) pin must be opened for use. (11) notes on energization to prevent the internal regulator ci rcuit from malfunctioning, set the vo ltage rise time during energization at 50 s or more (0.2 v to 2.7 v) . (12) initialization in the device, there are internal registers which are initializ ed only by a power-on reset. to initialize these registers, please turn on the power again. (13) directions of ?div a, ri? and ?divw a, rwi? instructions in the signed multiplication and division instructions (?div a, ri? and ?divw a, rwi?) , the value of the corresponding bank register (dtb, adb, usb, ssb) is set in ?00 h ?. if the values of the corresponding bank registers (dtb, adb, usb, ssb) are set to other than ?00 h ?, the remainder by the execution result of the instruction is not stored in the register of the instruction operand. (14) using realos the use of ei 2 os is not possible with the realos real time operating system. (15) caution on operatio ns during pll clock mode if the pll clock mode is selected, the microcontroller atte mpt to be working with the self-oscillating circuit even when there is no external oscillator or external clock in put is stopped. performance of this operation, however, cannot be guaranteed.
mb90435 series 18 ds07-13727-2e block diagram x0, x1 sot0 sck0 sin0 sot1 sck1 sin1 sot2 sck2 sin2 av cc av ss an0 to an7 avrh avrl adtg x0a, x1a rst hst f 2 mc 16lx cpu fmc-16 bus in0 to in5 in6/out2, in7/out3 out0, out1 tin0, tin1 ad00 to ad15 a16 to a23 ale rd wrl wrh hrq hak rdy clk int0 to int7 tot0, tot1 ppg0 to ppg3 clock controller ram 2 k/4 k/6 k/8 k rom/flash 64k/128 k/256 k (rom only) prescaler uart0 uart1 (sci) prescaler serial i/o 10-bit a/d converter 8 ch. prescaler 16-bit free-run timer 16-bit input capture 8 ch. 16-bit output compare 4 ch. 8/16-bit ppg 4 ch. 16-bit reload timer 2 ch. external bus interface external interrupt 8 ch.
mb90435 series ds07-13727-2e 19 memory map the memory space of the mb 90435 series is shown below. note : the high-order portion of bank 00 gives the image of the ff bank rom to make the small model of the c compiler effective. since the low-order 16 bits addres s are the same, the table in rom can be referenced without using the ?far? specification in the pointer declaration. for example, an attempt to access 00c000 h accesses the value at ffc000 h in rom.the rom area in bank ff exceeds 48 kbytes, and its entir e image cannot be shown in bank 00.the image between ff4000 h and ffffff h is visible in bank 00, while the image between ff0000 h and ff3fff h is visible only in bank ff. mb90v540g ffffff h feffff h ff0000 h fdffff h fe0000 h fcffff h fd0000 h 00ffff h 004000 h 003fff h 003900 h 0020ff h 001ff5 h 001ff0 h 000100 h 0000bf h 000000 h fc0000 h rom (ff bank) rom (fe bank) rom (fd bank) rom (fc bank) external rom (image of ff bank) peripheral external ram 8 k external peripheral rom correction mb90f438l (s)/438l (s) ffffff h feffff h ff0000 h fe0000 h 00ffff h 004000 h 003fff h 003900 h 002000 h 0010ff h 000100 h 0000bf h 000000 h rom (ff bank) rom (fe bank) external rom (image of ff bank) peripheral external ram 4 k external peripheral mb90f439 (s) /439 (s) fdffff h fcffff h fd0000 h fc0000 h rom (fd bank) rom (fc bank) ffffff h feffff h ff0000 h fe0000 h 00ffff h 004000 h 003fff h 003900 h 002100 h 0018ff h 000100 h 0000bf h 000000 h rom (ff bank) rom (fe bank) external rom (image of ff bank) peripheral external ram 6 k external peripheral ffffff h ff0000 h 00ffff h 004000 h 003fff h 003900 h 002000 h 0008ff h 000100 h 0000bf h rom (ff bank) rom (image of ff bank) peripheral external ram 2 k external peripheral mb90f437l (s) 000000 h external
mb90435 series 20 ds07-13727-2e i/o map (continued) address register abbreviation access resource name initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx b 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx b 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx b 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 07 h port 7 data register pdr7 r/w port 7 xxxxxxxx b 08 h port 8 data register pdr8 r/w port 8 xxxxxxxx b 09 h port 9 data register pdr9 r/w port 9 xxxxxxxx b 0a h port a data register pdra r/w port a _ _ _ _ _ _ _x b 0b h to 0f h reserved 10 h port 0 direction register ddr0 r/w port 0 0 0 0 0 0 0 0 0 b 11 h port 1 direction register ddr1 r/w port 1 0 0 0 0 0 0 0 0 b 12 h port 2 direction register ddr2 r/w port 2 0 0 0 0 0 0 0 0 b 13 h port 3 direction register ddr3 r/w port 3 0 0 0 0 0 0 0 0 b 14 h port 4 direction register ddr4 r/w port 4 0 0 0 0 0 0 0 0 b 15 h port 5 direction register ddr5 r/w port 5 0 0 0 0 0 0 0 0 b 16 h port 6 direction register ddr6 r/w port 6 0 0 0 0 0 0 0 0 b 17 h port 7 direction register ddr7 r/w port 7 0 0 0 0 0 0 0 0 b 18 h port 8 direction register ddr8 r/w port 8 0 0 0 0 0 0 0 0 b 19 h port 9 direction register ddr9 r/w port 9 0 0 0 0 0 0 0 0 b 1a h port a direction register ddra r/w port a _ _ _ _ _ _ _0 b 1b h analog input enable register ader r/w port 6, a/d 1 1 1 1 1 1 1 1 b 1c h port 0 pull-up control register pu cr0 r/w port 0 0 0 0 0 0 0 0 0 b 1d h port 1 pull-up control register pu cr1 r/w port 1 0 0 0 0 0 0 0 0 b 1e h port 2 pull-up control register pu cr2 r/w port 2 0 0 0 0 0 0 0 0 b 1f h port 3 pull-up control register pu cr3 r/w port 3 0 0 0 0 0 0 0 0 b 20 h serial mode control register 0 umc0 r/w uart0 0 0 0 0 0 1 0 0 b 21 h serial status register 0 usr0 r/w 0 0 0 1 0 0 0 0 b 22 h serial input data register 0/ serial output data register 0 uidr0/ uodr0 r/w xxxxxxxx b 23 h rate and data register 0 urd0 r/w 0 0 0 0 0 0 0x b
mb90435 series ds07-13727-2e 21 (continued) address register abbreviation access resource name initial value 24 h serial mode register 1 smr1 r/w uart1 0 0 0 0 0 0 0 0 b 25 h serial control register 1 scr1 r/w 0 0 0 0 0 1 0 0 b 26 h serial input data register 1/ serial output data register 1 sidr1/ sodr1 r/w xxxxxxxx b 27 h serial status register 1 ssr1 r/w 0 0 0 0 1_0 0 b 28 h uart1 prescaler control register u1cdcr r/w 0_ _ _1 1 1 1 b 29 h serial edge select register ses1 r/w _ _ _ _ _ _ _0 b 2a h prohibited 2b h serial i/o prescaler scdcr r/w extended i/o serial interface 0_ _ _1 1 1 1 b 2c h serial mode control register smcs r/w _ _ _ _0 0 0 0 b 2d h serial mode control register smcs r/w 0 0 0 0 0 0 1 0 b 2e h serial data register sdr r/w xxxxxxxx b 2f h serial edge select register ses2 r/w _ _ _ _ _ _ _0 b 30 h external interrupt enable register enir r/w external interrupt 0 0 0 0 0 0 0 0 b 31 h external interrupt req uest register eirr r/w xxxxxxxx b 32 h external interrupt level register elvr r/w 0 0 0 0 0 0 0 0 b 33 h external interrupt level register elvr r/w 0 0 0 0 0 0 0 0 b 34 h a/d control status register 0 adcs0 r/w a/d converter 0 0 0 0 0 0 0 0 b 35 h a/d control status register 1 adcs1 r/w 0 0 0 0 0 0 0 0 b 36 h a/d data register 0 adcr0 r xxxxxxxx b 37 h a/d data register 1 adcr1 r/w 0 0 0 0 1 _ xx b 38 h ppg0 operation mode control register ppgc0 r/w 16-bit programmable pulse generator 0/1 0 _ 0 0 0 _ _ 1 b 39 h ppg1 operation mode control register ppgc1 r/w 0 _ 0 0 0 0 0 1 b 3a h ppg0/1 clock selection register ppg01 r/w 0 0 0 0 0 0 _ _ b 3b h prohibited 3c h ppg2 operation mode control register ppgc2 r/w 16-bit programmable pulse generator 2/3 0 _ 0 0 0 _ _1 b 3d h ppg3 operation mode control register ppgc3 r/w 0 _ 0 0 0 0 0 1 b 3e h ppg2/3 clock selection register ppg23 r/w 0 0 0 0 0 0 _ _ b 3f h prohibited 40 h ppg4 operation mode control register ppgc4 r/w 16-bit programmable pulse generator 4/5 0 _ 0 0 0 _ _ 1 b 41 h ppg5 operation mode control register ppgc5 r/w 0 _ 0 0 0 0 0 1 b 42 h ppg4/5 clock selection register ppg45 r/w 0 0 0 0 0 0 _ _ b 43 h prohibited 44 h ppg6 operation mode control register ppgc6 r/w 16-bit programmable pulse generator 6/7 0 _ 0 0 0 _ _ 1 b 45 h ppg7 operation mode control register ppgc7 r/w 0 _ 0 0 0 0 0 1 b 46 h ppg6/7 clock selection register ppg67 r/w 0 0 0 0 0 0 _ _ b
mb90435 series 22 ds07-13727-2e (continued) address register abbreviation access resource name initial value 47 h to 4b h prohibited 4c h input capture control status register 0/1 ics01 r/w input capture 0/1 0 0 0 0 0 0 0 0 b 4d h input capture control status register 2/3 ics23 r/w input capture 2/3 0 0 0 0 0 0 0 0 b 4e h input capture control status register 4/5 ics45 r/w input capture 4/5 0 0 0 0 0 0 0 0 b 4f h input capture control status register 6/7 ics67 r/w input capture 6/7 0 0 0 0 0 0 0 0 b 50 h timer control status register 0 tmcsr0 r/w 16-bit reload timer 0 0 0 0 0 0 0 0 0 b 51 h timer control status register 0 tmcsr0 r/w _ _ _ _ 0 0 0 0 b 52 h timer register 0/reload register 0 tmr0/ tmrlr0 r/w xxxxxxxx b 53 h timer register 0/reload register 0 tmr0/ tmrlr0 r/w xxxxxxxx b 54 h timer control status register 1 tmcsr1 r/w 16-bit reload timer 1 0 0 0 0 0 0 0 0 b 55 h timer control status register 1 tmcsr1 r/w _ _ _ _ 0 0 0 0 b 56 h timer register 1/reload register 1 tmr1/ tmrlr1 r/w xxxxxxxx b 57 h timer register 1/reload register 1 tmr1/ tmrlr1 r/w xxxxxxxx b 58 h output compare control status register 0 ocs0 r/w output compare 0/1 0 0 0 0 _ _ 0 0 b 59 h output compare control status register 1 ocs1 r/w _ _ _0 0 0 0 0 b 5a h output compare control status register 2 ocs2 r/w output compare 2/3 0 0 0 0 _ _ 0 0 b 5b h output compare control status register 3 ocs3 r/w _ _ _ 0 0 0 0 0 b 5c h to 6b h prohibited 6c h timer counter data register tcdt r/w i/o timer 0 0 0 0 0 0 0 0 b 6d h timer counter data register tcdt r/w 0 0 0 0 0 0 0 0 b 6e h timer counter control status r egister tccs r/w 0 0 0 0 0 0 0 0 b 6f h rom mirror function selection register romm r/w rom mirror _ _ _ _ _ _ _ 1 b 70 h to 7f h reserved 80 h to 8f h reserved 90 h to 9d h prohibited 9e h program address detection control status register pacsr r/w address match detection function 0 0 0 0 0 0 0 0 b 9f h delayed interrupt/release register dirr r/w delayed interrupt _ _ _ _ _ _ _ 0 b a0 h low-power mode control register lpmcr r/w low power controller 0 0 0 1 1 0 0 0 b a1 h clock selection register ckscr r/w low power controller 1 1 1 1 1 1 0 0 b
mb90435 series ds07-13727-2e 23 (continued) address register abbreviation access resource name initial value a2 h to a4 h prohibited a5 h automatic ready function select register arsr w external memory access 0 0 1 1 _ _ 0 0 b a6 h external address output control register hacr w 0 0 0 0 0 0 0 0 b a7 h bus control signal selection register ecsr w 0 0 0 0 0 0 0 _ b a8 h watchdog timer control register wdtc r/w watchdog timer xxxxx 1 1 1 b a9 h time base timer control register tbtc r/w time base timer 1 - - 0 0 1 0 0 b aa h watch timer control register wtc r/w watch timer 1 x 0 0 0 0 0 0 b ab h to ad h prohibited ae h flash memory control status register (flash only, otherwise reserved) fmcs r/w flash memory 0 0 0 x 0 0 0 0 b af h prohibited b0 h interrupt control register 00 icr00 r/w interrupt controller 0 0 0 0 0 1 1 1 b b1 h interrupt control register 01 icr01 r/w 0 0 0 0 0 1 1 1 b b2 h interrupt control register 02 icr02 r/w 0 0 0 0 0 1 1 1 b b3 h interrupt control register 03 icr03 r/w 0 0 0 0 0 1 1 1 b b4 h interrupt control register 04 icr04 r/w 0 0 0 0 0 1 1 1 b b5 h interrupt control register 05 icr05 r/w 0 0 0 0 0 1 1 1 b b6 h interrupt control register 06 icr06 r/w 0 0 0 0 0 1 1 1 b b7 h interrupt control register 07 icr07 r/w 0 0 0 0 0 1 1 1 b b8 h interrupt control register 08 icr08 r/w 0 0 0 0 0 1 1 1 b b9 h interrupt control register 09 icr09 r/w 0 0 0 0 0 1 1 1 b ba h interrupt control register 10 icr10 r/w 0 0 0 0 0 1 1 1 b bb h interrupt control register 11 icr11 r/w 0 0 0 0 0 1 1 1 b bc h interrupt control register 12 icr12 r/w 0 0 0 0 0 1 1 1 b bd h interrupt control register 13 icr13 r/w 0 0 0 0 0 1 1 1 b be h interrupt control register 14 icr14 r/w 0 0 0 0 0 1 1 1 b bf h interrupt control register 15 icr15 r/w 0 0 0 0 0 1 1 1 b c0 h to ff h external
mb90435 series 24 ds07-13727-2e (continued) address register abbreviation access resource name initial value 1ff0 h program address detec- tion register 0 padr0 r/w address match detection function xxxxxxxx b 1ff1 h program address detec- tion register 0 padr0 r/w xxxxxxxx b 1ff2 h program address detec- tion register 0 padr0 r/w xxxxxxxx b 1ff3 h program address detec- tion register 1 padr1 r/w xxxxxxxx b 1ff4 h program address detec- tion register 1 padr1 r/w xxxxxxxx b 1ff5 h program address detec- tion register 1 padr1 r/w xxxxxxxx b 3900 h reload l prll0 r/w 16-bit programmable pulse generator 0/1 xxxxxxxx b 3901 h reload h prlh0 r/w xxxxxxxx b 3902 h reload l prll1 r/w xxxxxxxx b 3903 h reload h prlh1 r/w xxxxxxxx b 3904 h reload l prll2 r/w 16-bit programmable pulse generator 2/3 xxxxxxxx b 3905 h reload h prlh2 r/w xxxxxxxx b 3906 h reload l prll3 r/w xxxxxxxx b 3907 h reload h prlh3 r/w xxxxxxxx b 3908 h reload l prll4 r/w 16-bit programmable pulse generator 4/5 xxxxxxxx b 3909 h reload h prlh4 r/w xxxxxxxx b 390a h reload l prll5 r/w xxxxxxxx b 390b h reload h prlh5 r/w xxxxxxxx b 390c h reload l prll6 r/w 16-bit programmable pulse generator 6/7 xxxxxxxx b 390d h reload h prlh6 r/w xxxxxxxx b 390e h reload l prll7 r/w xxxxxxxx b 390f h reload h prlh7 r/w xxxxxxxx b 3910 h to 3917 h reserved 3918 h input capture register 0 ipcp0 r input capture 0/1 xxxxxxxx b 3919 h input capture register 0 ipcp0 r xxxxxxxx b 391a h input capture register 1 ipcp1 r xxxxxxxx b 391b h input capture register 1 ipcp1 r xxxxxxxx b 391c h input capture register 2 ipcp2 r input capture 2/3 xxxxxxxx b 391d h input capture register 2 ipcp2 r xxxxxxxx b 391e h input capture register 3 ipcp3 r xxxxxxxx b 391f h input capture register 3 ipcp3 r xxxxxxxx b
mb90435 series ds07-13727-2e 25 (continued) read/write notation initial value notation note : any write access to reserved addresses in i/ o map should not be performed. a read access to reserved addresses results in reading ?x?. address register abbreviation access resource name initial value 3920 h input capture register 4 ipcp4 r input capture 4/5 xxxxxxxx b 3921 h input capture register 4 ipcp4 r xxxxxxxx b 3922 h input capture register 5 ipcp5 r xxxxxxxx b 3923 h input capture register 5 ipcp5 r xxxxxxxx b 3924 h input capture register 6 ipcp6 r input capture 6/7 xxxxxxxx b 3925 h input capture register 6 ipcp6 r xxxxxxxx b 3926 h input capture register 7 ipcp7 r xxxxxxxx b 3927 h input capture register 7 ipcp7 r xxxxxxxx b 3928 h output compare register 0 occp0 r/w output compare 0/1 xxxxxxxx b 3929 h output compare register 0 occp0 r/w xxxxxxxx b 392a h output compare register 1 occp1 r/w xxxxxxxx b 392b h output compare register 1 occp1 r/w xxxxxxxx b 392c h output compare register 2 occp2 r/w output compare 2/3 xxxxxxxx b 392d h output compare register 2 occp2 r/w xxxxxxxx b 392e h output compare register 3 occp3 r/w xxxxxxxx b 392f h output compare register 3 occp3 r/w xxxxxxxx b 3930 h to 39ff h reserved 3a00 h to 3aff h reserved 3b00 h to 3bff h reserved 3c00 h to 3cff h reserved 3d00 h to 3dff h reserved 3e00 h to 3fff h reserved r/w : reading and writing permitted r : read-only w : write-only 0 : initial value is ?0?. 1 : initial value is ?1?. x : initial value is undefined.
mb90435 series 26 ds07-13727-2e interrupt map interrupt cause ei 2 os clear interrupt vector interrupt control register number address number address reset n/a #08 ffffdc h ?? int9 instruction n/a #09 ffffd8 h ?? exception n/a #10 ffffd4 h ?? reserved n/a #11 ffffd0 h icr00 0000b0 h reserved n/a #12 ffffcc h reserved n/a #13 ffffc8 h icr01 0000b1 h reserved n/a #14 ffffc4 h external interrupt int0/int1 *1 #15 ffffc0 h icr02 0000b2 h time base timer n/a #16 ffffbc h 16-bit reload timer 0 *1 #17 ffffb8 h icr03 0000b3 h 8/10-bit a/d converter *1 #18 ffffb4 h i/o timer n/a #19 ffffb0 h icr04 0000b4 h external interrupt int2/int3 *1 #20 ffffac h serial i/o *1 #21 ffffa8 h icr05 0000b5 h 8/16-bit ppg 0/1 n/a #22 ffffa4 h input capture 0 *1 #23 ffffa0 h icr06 0000b6 h external interrupt int4/int5 *1 #24 ffff9c h input capture 1 *1 #25 ffff98 h icr07 0000b7 h 8/16-bit ppg 2/3 n/a #26 ffff94 h external interrupt int6/int7 *1 #27 ffff90 h icr08 0000b8 h watch timer n/a #28 ffff8c h 8/16-bit ppg 4/5 n/a #29 ffff88 h icr09 0000b9 h input capture 2/3 *1 #30 ffff84 h 8/16-bit ppg 6/7 n/a #31 ffff80 h icr10 0000ba h output compare 0 *1 #32 ffff7c h output compare 1 *1 #33 ffff78 h icr11 0000bb h input capture 4/5 *1 #34 ffff74 h output compare 2/3 - input capture 6/7 *1 #35 ffff70 h icr12 0000bc h 16-bit reload timer 1 *1 #36 ffff6c h uart 0 rx *2 #37 ffff68 h icr13 0000bd h uart 0 tx *1 #38 ffff64 h uart 1 rx *2 #39 ffff60 h icr14 0000be h uart 1 tx *1 #40 ffff5c h flash memory n/a #41 ffff58 h icr15 0000bf h delayed interrupt n/a #42 ffff54 h
mb90435 series ds07-13727-2e 27 *1 : the interrupt request flag is cleared by the ei 2 os interrupt clear signal. *2 : the interrupt request flag is cleared by the ei 2 os interrupt clear signal. a stop request is available. notes : ? n/a : the interrupt request fl ag is not cleared by the ei 2 os interrupt clear signal. ? for a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the ei 2 os interrupt clear signal. ? at the end of ei 2 os, the ei 2 os clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. if one interrupt flag starts the ei 2 os and in the meantime another interrupt flag is set by a hardware event, the later event is lost because the flag is cleared by the ei 2 os clear signal caused by the first event. so it is re commended not to use the ei 2 os for this interrupt number. ? if ei 2 os is enabled, ei 2 os is initiated when one of the two interr upt signals in the same interrupt control register (icr) is asserted. this means that different interrupt sources share the same ei 2 os descriptor which should be unique for each in terrupt source. for this reason, w hen one interrupt source uses the ei 2 os, the other interrupt should be disabled.
mb90435 series 28 ds07-13727-2e electrical characteristics 1. absolute maximum ratings (v ss = av ss = 0.0 v) *1 : av cc , avrh, avrl should not exceed v cc . also, avrh, avrl should not exceed av cc , and avrl does not exceed avrh. *2 : v i and v o should not exceed v cc + 0.3 v. v i should not exceed the specified ratings. however if the maximum current to/from an input is limited by some means with external components, the i clamp rating supercedes the v i rating. *3 : the maximum output current is a peak value for a corresponding pin. *4 : average output current is an average current val ue observed for a 100 ms period for a corresponding pin. *5 : total average current is an average current valu e observed for a 100 ms peri od for all corresponding pins. *6 : ? applicable to pins : p00 to p07, p1 0 to p17, p20 to p27, p30 to p37, p 40 to p47, p50 to p57, p60 to p67, p70 to p77, p80 to p87, p90 to p97, pa0 ? use within recommended operating conditions. ? use at dc voltage (current) . ? the + b signal should always be applied with a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values , either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective di ode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a + b signal is input when the microcon troller current is off (not fixe d at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the powe r supply is provided from the pins and the resulting supply voltage may not be su fficient to operate the power-on result. (continued) parameter symbol value units remarks min max power supply voltage v cc v ss ? 0.3 v ss + 6.0 v av cc v ss ? 0.3 v ss + 6.0 v v cc = av cc * 1 avrh, avrl v ss ? 0.3 v ss + 6.0 v av cc avrh/avrl, avrh avrl* 1 input voltage v i v ss ? 0.3 v ss + 6.0 v *2 output voltage v o v ss ? 0.3 v ss + 6.0 v *2 maximum clamp current i clamp ? 2.0 + 2.0 ma *6 total maximum clamp current | i clamp | ? 20 ma *6 ?l? level max output current i ol ? 15 ma *3 ?l? level avg. output current i olav ? 4ma*4 ?l? level max overall output current i ol ? 100 ma ?l? level avg. overall output current i olav ? 50 ma *5 ?h? level max output current i oh ?? 15 ma *3 ?h? level avg. output current i ohav ?? 4ma*4 ?h? level max overall output current i oh ?? 100 ma ?h? level avg. overall output current i ohav ?? 50 ma *5 power consumption p d ? 500 mw flash device ? 400 mw mask rom operating temperature t a ? 40 + 105 c storage temperature t stg ? 55 + 150 c
mb90435 series ds07-13727-2e 29 (continued) ? care must be taken not to leave the + b input pin open. ? note that analog system input/outpu t pins other than the a/d input pins (lcd drive pins, comparator input pins, etc.) cannot accept + b signal input. ? sample recommended circuits : note : average output current = operating current operating efficiency warning: semiconductor devices can be permanently dama ged by application of stress (voltage, current, temperature, etc.) in excess of absolute ma ximum ratings. do not exceed these ratings. p-ch n-ch v cc r input/output equivalent circuits + b input (0 v to 16 v) limiting resistance protective diode
mb90435 series 30 ds07-13727-2e 2. recommended conditions (v ss = av ss = 0.0 v) *: use a ceramic capacitor or a capacitor of better 4. ac characteristics. the v cc capacitor should be greater than this capacitor. warning: the recommended operating co nditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outs ide the listed conditions are advised to contact their representatives beforehand. parameter symbol value units remarks min typ max power supply voltage v cc , av cc 4.5 5.0 5.5 v under normal operation : mb90f439 (s) /439 (s) /v540g 3.5 5.0 5.5 v under normal operation : mb90f438l (s) /437l (s) /438l (s) 3.0 ? 5.5 v maintain ram data in stop mode smooth capacitor c s 0.022 0.1 1.0 f* operating temperature t a ? 40 ?+ 105 c c c s c pin connection diagram
mb90435 series ds07-13727-2e 31 3. dc characteristics (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (continued) parameter sym- bol pin name condition value units remarks min typ max input h voltage v ihs cmos hysteresis input pin ? 0.8 v cc ? v cc + 0.3 v v ih ttl input pin ? 2.0 ?? v v ihm md input pin ? v cc ? 0.3 ? v cc + 0.3 v input l voltage v ils cmos hysteresis input pin ? v cc ? 0.3 ? 0.2 v cc v v il ttl input pin ??? 0.8 v v ilm md input pin ? v ss ? 0.3 ? v cc + 0.3 v output h voltage v oh all output pins v cc = 4.5 v, i oh = ? 4.0 ma v cc ? 0.5 ?? v output l voltage v ol all output pins v cc = 4.5 v, i ol = 4.0 ma ?? 0.4 v input leak current i il ? v cc = 5.5 v, v ss < v i < v cc ? 5 ? 5 a pull-up resistance r up p00 to p07, p10 to p17, p20 to p27, p30 to p37, rst ? 25 50 100 k ? pull-down resistance r do wn md2 ? 25 50 100 k ?
mb90435 series 32 ds07-13727-2e (continued) (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) * : the power supply current testing cond itions are when using the external clock. parameter sym- bol pin name condition value units remarks min typ max power supply current* i cc v cc internal frequency : 16 mhz, at normal operating ? 40 55 ma internal frequency : 16 mhz, at flash programming/erasing ? 50 70 ma flash device i ccs internal frequency : 16 mhz, at sleep mode ? 12 20 ma i cts v cc = 5.0 v 1 % , internal frequency : 2 mhz, at pseudo timer mode ? 300 600 a ? 600 1100 a mb90f348l (s) ? 200 400 a mb90437l (s) / 438l (s) i ccl internal frequency : 8 khz, at sub operation, t a = 25 c ? 400 750 a mb90f438l (s) ? 50 100 amask rom ? 150 300 a flash device i ccls internal frequency : 8 khz, at sub sleep, t a = 25 c ? 15 40 a i cct internal frequency : 8 khz, at timer mode, t a = 25 c ? 725 a i cch1 at stop, t a = 25 c ? 520 a i cch2 at hardware standby mode, t a = 25 c ? 50 100 a input capacity c in other than av cc , av ss , avrh, avrl, c, v cc , v ss ?? 515pf
mb90435 series ds07-13727-2e 33 4. ac characteristics (1) clock timing (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin name value units remarks min typ max oscillation frequency f c x0, x1 3 ? 16 mhz v cc = 5.0 v 10 % 3 ? 5mhz v cc < 4.5 (mb90f438l (s) / 437l (s) /438l (s) ) f cl x0a, x1a ? 32.768 ? khz oscillation cycle time t cyl x0, x1 62.5 ? 333 ns v cc = 5.0 v 10 % 200 ? 333 ns v cc < 4.5 (mb90f438l (s) / 437l (s) /438l (s) ) t lcyl x0a, x1a ? 30.5 ? s input clock pulse width p wh , p wl x0 10 ?? ns duty ratio is about 30 % to 70 % . p wlh , p wll x0a ? 15.2 ? s input clock rise and fall time t cr , t cf x0 ?? 5 ns when using external clock machine clock frequency f cp ? 1.5 ? 16 mhz when using main clock f lcp ?? 8.192 ? khz when using sub-clock machine clock cycle time t cp ? 62.5 ? 666 ns when using main clock t lcp ?? 122.1 ? s when using sub-clock x0 t cyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t lcyl t cf t cr 0.8 v cc 0.2 v cc p wlh p wll clock timing
mb90435 series 34 ds07-13727-2e 5.5 3.5 1.5 816 guaranteed operation range (mb90f438l(s)/437l(s)/438l(s)) guaranteed pll operation range (mb90f438l(s)/437l(s)/438l(s)) 4.5 guaranteed operation range (mb90f439(s)/439(s)/v540g) guaranteed pll operation range ( mb90f439(s)/439(s)/v540g) power supply voltage v cc (v) machine clock f cp (mhz) guaranteed pll operation range 16 12 8 9 4 34 8 16 4 3 2 1 pll off external clock frequency and machine clock frequency machine clock f cp (mhz) external clock f c (mhz)
mb90435 series ds07-13727-2e 35 ac characteristics are set to the me asured reference voltage values below. 0.8 v cc 0.2 v cc 2.4 v 0.8 v 2.0 v 0.8 v input signal waveform output signal waveform hysteresis input pin ttl input pin output pin
mb90435 series 36 ds07-13727-2e (2) clock output timing (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (3) reset and hardware standby input timing (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) ?t cp ? represents one cycle time of the machine clock. oscillation time of oscillator is time that amplitude reached the 90 % . in the crystal oscillator, the oscillation time is between several ms to tens of ms. in ceramic os cillator, the oscillation time is between handreds of s to several ms. in the external clock, the oscillation time is 0 ns. any reset can not fully initialize the flash memory if it is perf orming the automatic algorithm. parameter symbol pin name condition value units remarks min max cycle time t cyc clk v cc = 5 v 10 % 62.5 ? ns clk clk t chcl 20 ? ns parameter symbol pin name value units remarks min max reset input time t rstl rst 4 t cp ? ns under normal operation oscillation time of oscillator + 4 t cp ? ms in stop mode 100 ? s pseudo timer mode (mb90437l (s) /438l (s) ) 4 t cp ? ns pseudo timer mode (other than mb90437l (s) /438l (s) ) 2 t cp ? s in sub clock mode, sub sleep mode and watch mode hardware standby input time t hstl hst 4 t cp ? ns under normal operation clk t cyc 2.4 v 2.4 v 0.8 v t chcl
mb90435 series ds07-13727-2e 37 rst hst 0.2 v cc t rstl , t hstl 0.2 v cc t rstl 0.2 v cc 0.2 v cc 4 t cp rst x0 internal operation clock internal reset 90% of amplitude oscillation time of oscillator oscillation setting time instruction execution under normal operation, pseudo timer mode , sub clock mode, sub sleep mode, watch mode in stop mode
mb90435 series 38 ds07-13727-2e (4) power on reset (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) * : v cc must be kept lower than 0.2 v before power-on. notes : ? the above values are used for creating a power-on reset. ? some registers in the device are initialized only upon a power-on reset. to initialize these register, turn on the power supply using the above values. parameter symbol pin name condition value units remarks min max power on rise time t r v cc ? 0.05 30 ms * power off time t off v cc 50 ? ms due to repetitive operation v cc v cc v ss 3.0 v t r t off 2.7 v 0.2 v 0.2 v 0.2 v ram data being held it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower. sudden changes in the power supply voltage ma y cause a power-on reset. to change the power supply volt age while the device is in oper ation, it is recommended to raise the voltage smoothly to suppr ess fluctuations as shown below. in this case, change the supply voltage with the pll clock not used. if the voltage drop is 1 v or fewer per second, howeve r, you can use the pll clock.
mb90435 series ds07-13727-2e 39 (5) bus timing (read) (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin name condition value units remarks min max ale pulse width t lhll ale ? t cp /2 ? 20 ? ns valid address ale time t avll ale, a16 to a23, ad00 to ad15 t cp /2 ? 20 ? ns ale address valid time t llax ale, ad00 to ad15 t cp /2 ? 15 ? ns valid address rd time t avrl a16 toa23, ad00 to ad15, rd t cp ? 15 ? ns valid address valid data input t avdv a16 to a23, ad00 to ad15 ? 5 t cp /2 ? 60 ns rd pulse width t rlrh rd 3 t cp /2 ? 20 ? ns rd valid data input t rldv rd , ad00 to ad15 ? 3 t cp /2 ? 60 ns rd data hold time t rhdx rd , ad00 to ad15 0 ? ns rd ale time t rhlh rd , ale t cp /2 ? 15 ? ns rd address valid time t rhax rd , a16 to a23 t cp /2 ? 10 ? ns valid address clk time t avch a16 to a23, ad00 to ad15, clk t cp /2 ? 20 ? ns rd clk time t rlch rd , clk t cp /2 ? 20 ? ns ale rd time t llrl ale, rd t cp /2 ? 15 ? ns
mb90435 series 40 ds07-13727-2e 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.2 v cc 0.8 v cc 0.2 v cc 0.8 v cc clk ale rd a16 to a23 ad00 to ad15 2.4 v t avch t lhll t rhlh t avll t avrl t rldv t rlrh t rhax t rhdx t llax t llrl t rlch t avdv address read data bus timing (read)
mb90435 series ds07-13727-2e 41 (6) bus timing (write) (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin name condition value units remarks min max valid address wr time t avwl a16 to a23 ad00 to ad15, wr ? t cp ? 15 ? ns wr pulse width t wlwh wr 3 t cp /2 ? 20 ? ns valid data output wr time t dvwh ad00 to ad15, wr 3 t cp /2 ? 20 ? ns wr data hold time t whdx ad00 to ad15, wr 20 ? ns wr address valid time t whax a16 to a23, wr t cp /2 ? 10 ? ns wr ale time t whlh wr , ale t cp /2 ? 15 ? ns wr clk time t wlch wr , clk t cp /2 ? 20 ? ns 0.8 v 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v clk ale wr (wrl, wrh) a16 to a23 ad00 to ad15 t whlh t avwl t wlwh t whax t whdx t wlch t dvwh address write data bus timing (write)
mb90435 series 42 ds07-13727-2e (7) ready input timing (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) note : if the rdy setup time is insu fficient, use the auto-ready function. parameter symbol pin name condition value units remarks min max rdy setup time t ryhs rdy ? 45 ? ns rdy hold time t ryhh rdy 0 ? ns t ryhs t ryhh 2.4 v 0.8 v cc 0.2 v cc 0.8 v cc clk ale rd/wr rdy no wait is used. rdy when wait is used (1 cycle). ready input timing
mb90435 series ds07-13727-2e 43 (8) hold timing (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) note : there is more than 1 cycle from t he time hrq is read to the time the hak is changed. (9) uart0/1, serial i/o timing (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) notes : ? ac characteristic in clk synchronized mode. ? c l is load capacity value of pins when testing. ? for t cp (machine clock cycle time) , refer to ? (1) clock timing?. parameter symbol pin name condition value units remarks min max pin floating hak time t xhal hak ? 30 t cp ns hak time pin valid time t hahv hak t cp 2 t cp ns parameter symbol pin name condition value units remarks min max serial clock cycle time t scyc sck0 to sck2 internal clock opera- tion output pins are c l = 80 pf + 1 ttl. 8 t cp ? ns sck sot delay time t slov sck0 to sck2, sot0 to sot2 ? 80 80 ns valid sin sck t ivsh sck0 to sck2, sin0 to sin2 100 ? ns sck valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ? ns serial clock ?h? pulse width t shsl sck0 to sck2 external clock oper- ation output pins are c l = 80 pf + 1 ttl. 4 t cp ? ns serial clock ?l? pulse width t slsh sck0 to sck2 4 t cp ? ns sck sot delay time t slov sck0 to sck2, sot0 to sot2 ? 150 ns valid sin sck t ivsh sck0 to sck2, sin0 to sin2 60 ? ns sck valid sin hold time t shix sck0 to sck2, sin0 to sin2 60 ? ns hak t xhal t hahv 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v each pin high impedance hold timing
mb90435 series 44 ds07-13727-2e sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc internal shift clock mode sck sot sin t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc external shift clock mode
mb90435 series ds07-13727-2e 45 (10) timer input timing (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (11) timer output timing (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin name condition value units remarks min max input pulse width t tiwh tin0, tin1 ? 4 t cp ? ns t tiwl in0 to in7 parameter symbol pin name condition value units remarks min max clk t out change time t to tot0 to tot1, ppg0 to ppg3 ? 30 ? ns 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl timer input timing clk t out 2.4 v t to 2.4 v 0.8 v timer output timing
mb90435 series 46 ds07-13727-2e (12) trigger input timing (mb90f438l (s) /437l (s) /438l (s) : v cc = 3.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) (mb90f439 (s) /439 (s) /v540g : v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 105 c) parameter symbol pin name condition value units remarks min max input pulse width t trgh t trgl int0 to int7, adtg ? 5 t cp ? ns under nomal operation 1 ? s in stop mode 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl trigger input timing
mb90435 series ds07-13727-2e 47 5. a/d converter electrical characteristics ( v cc = av cc = 5.0 v 10 % , v ss = av ss = 0.0 v , 3.0 v avrh ? avrl , t a = ? 40 c to + 105 c) * : when not using an a/d converter, this is the current (v cc = av cc = avrh = 5.0 v) when the cpu is stopped. note: the functionality of the a/d converter is only guaranteed for vcc = 5.0 v 10 % (also for mb90f438l (s) / 437l (s) /438l (s) ) . parameter symbol pin name value units remarks min typ max resolution ?? ? ? 10 bit conversion error ?? ? ? 5.0 lsb nonlinearity error ?? ? ? 2.5 lsb differential nonlinearity error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an7 avrl ? 3.5 lsb avrl + 0.5 lsb avrl + 4.5 lsb v 1 lsb = (avrh- av ss )/1024 full scale transition voltage v fst an0 to an7 avrh ? 6.5 lsb avrh ? 1.5 lsb avrh + 1.5 lsb v compare time ?? 352 t cp ?? ns internal frequency : 16 mhz sampling time ?? 64 t cp ?? ns internal frequency : 16 mhz analog port input current i ain an0 to an7 ? 1 ? 1 a v cc = av cc = 5.0 v 1 % analog input voltage range v ain an0 to an7 avrl ? avrh v reference voltage range ? avrh avrl + 2.7 ? av cc v ? avrl 0 ? avrh ? 2.7 v power supply current i a av cc ? 5 ? ma i ah av cc ?? 5 a* reference voltage supply current i r avrh ? 400 600 a flash device ? 140 260 a mask rom i rh avrh ?? 5 a* offset between input channels ? an0 to an7 ?? 4lsb
mb90435 series 48 ds07-13727-2e a/d converter glossary resolution : analog changes that are identifiable with the a/d converter linearity error : the deviation of the straight line connecting the zero transition point (?00 0000 0000? ?00 0000 0001?) with the full-scale transition point (?11 1111 1110? ?11 1111 1111?) from actual conversion characteristics differential linearity error : the deviation of input volt age needed to change the output code by 1 lsb from the theoretical value total error : the total error is defined as a difference bet ween the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error. (continued) 3ff 3fe 3fd 004 003 002 001 avrl avrh v nt 0.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} analog input digital output total error actual conversion value actual conversion characteristics (measured value) theoretical characteristics [v] avrh ? avrl 1024 1 lsb = (theoretical value) v ot (theoretical value) = avrl + 0.5 lsb [v] v fst (theoretical value) = avrh ? 1.5 lsb [v] total error for digital output n = [lsb] v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb v nt : voltage at a transition of digital output from (n ? 1) to n
mb90435 series ds07-13727-2e 49 (continued) notes on using a/d converter select the output impedance value for the external circuit of analog input according to the following conditions, : output impedance values of the external circuit of 15 k ? or lower are recommended. when capacitors are connected to external pins, t he capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. note : when the output impedance of the external circui t is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 mhz) . error the smaller the | avrh ? avrl |, the greater the erro r would become relatively. 3ff 3fe 3fd 004 003 002 001 avrl avrh avrl avrh n + 1 n n ? 1 n ? 2 v nt v nt v ( n + 1) t v ot v fst {1 lsb (n ? 1) + v ot } digital output digital output linearity error differential linearity error analog input analog input actual conversion value (measured value) actual conversion characteristics theoretical characteristics (measured value) theorential characteristics actual conversion value (measured value) (measured value) acturel conversion value linearity error of digital output n [lsb] v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [v] v fst ? v ot 1022 1 lsb ? 1 lsb [lsb] v ( n + 1 ) t ? v nt 1 lsb differential linearity error of digital n v ot : voltage at transition of digital output from ?000 h ? to ?001 h ? v fst : voltage at transition of digital output from ?3fe h ? to ?3ff h ? = = = 3.2 k ? max. 30 pf max. analog input comparator equipment of analog input circuit model
mb90435 series 50 ds07-13727-2e 6. flash memory program/erase characteristics parameter condition value units remarks min typ max sector erase time t a = + 25 c v cc = 5.0 v ? 1 15 s excludes 00 h programming prior erasure chip erase time ? 5 ? s mb90f438l (s) excludes 00 h programming prior erasure 7 ? s mb90f439 (s) word (16 bit width) programming time ? 16 3,600 s excludes system-level overhead erase/program cycle ? 10,000 ?? cycle
mb90435 series ds07-13727-2e 51 example characteristics 5 4.5 4 3 .5 3 2.5 2 1.5 1 0.5 0 0 -10 - 8 -6 -4 -2 i oh [ma] v oh [v] v oh ? i oh 0.9 0. 8 0.7 0.6 0.5 0.4 0. 3 0.2 0.1 0 0 10 8 6 4 2 i ol [ma] v ol [v] v ol ? i ol (v cc = 4.5 v, t a = +25c) (v cc = 4.5 v, t a = +25c) 5 4 3 2 1 0 3 5.5 5 4.5 4 3 .5 vcc [v] vin [v] vin ? vcc 6 6.5 v ih v il (t a =+25c) ? ?h? level output voltage ? ?h? level input voltage/ ?l? level input voltage (hysterisis inpiut) ? ?l? level output voltage
mb90435 series 52 ds07-13727-2e ? power supply current (mb90439) 40 35 30 25 20 15 10 5 0 27 6 5 4 3 vcc [v] icc [ma] icc ? vcc fcp = 12 mhz fcp = 16 mhz fcp = 10 mhz fcp = 8 mhz fcp = 4 mhz fcp = 2 mhz 12 10 8 6 4 2 0 27 6 5 4 3 vcc [v] icc [ma] iccs ? vcc fcp = 12 mhz fcp = 16 mhz fcp = 10 mhz fcp = 8 mhz fcp = 4 mhz fcp = 2 mhz 600 500 400 300 200 100 0 27 6 5 4 3 vcc [v] i cts [ a] i cts ? v cc fcp = 2 mhz 60 50 40 30 20 10 0 27 6 5 4 3 vcc [v] i ccl [ a] i ccl ? v cc fcp = 8 khz 70 80 90 100 (ta = +25?c) (ta = +25?c) (ta = +25?c) (ta = +25?c)
mb90435 series ds07-13727-2e 53 40 35 30 25 20 15 10 5 0 vcc [v] i ccls [ a] i ccls ? v cc fcp = 8 khz 25 20 15 10 5 0 2 7 6 5 4 3 vcc [v] i cct [ a] i cct ? v cc 20 15 10 5 0 27 6 5 4 3 vcc [v] i cch1 [ a] i cch1 ? v cc 2 7 6 5 4 3 (stop, ta = +25?c) (ta = +25?c) (ta = +25?c) fcp = 8 khz
mb90435 series 54 ds07-13727-2e ? power supply current (mb90f439) 45 40 35 30 25 20 15 10 5 0 23456 fcp = 8 mhz fcp = 4 mhz fcp = 2 mhz fcp = 16 mhz fcp = 12 mhz fcp = 10 mhz icc ? vcc i cc [ma] v cc [v] 14 12 10 8 6 4 2 0 23456 iccs ? vcc i cc [ma] v cc [v] 600 500 400 300 200 100 0 23456 fcp = 2 mhz i cts ? v cc i cts [ a] v cc [v] 300 250 200 150 100 50 0 23456 fcp = 8 khz i ccl ? v cc i ccl [ a] v cc [v] 7 7 7 7 (ta = +25 ?c) (ta = +25 ?c) (ta = +25 ?c) (ta = +25 ?c) fcp = 8 mhz fcp = 4 mhz fcp = 2 mhz fcp = 16 mhz fcp = 12 mhz fcp = 10 mhz
mb90435 series ds07-13727-2e 55 45 40 35 30 25 20 15 10 5 0 23456 fcp = 8 mhz i ccls ? v cc i ccls [ a] v cc [v] 7 25 20 15 10 5 0 23456 i cct ? v cc i cct [ a] v cc [v] 7 100 90 85 70 60 50 40 30 20 0 23456 i cch2 ? v cc i cch2 [ a] v cc [v] 7 10 (hardware standby, ta = +25 ?c) (ta = +25 ?c) (ta = +25 ?c) fcp = 8 mhz 20 15 10 5 0 27 6 5 4 3 vcc [v] i cch1 [ a] i cch1 ? v cc (stop, ta = +25?c)
mb90435 series 56 ds07-13727-2e ordering information part number package remarks mb90f438lpf mb90f438lspf mb90f439pf mb90f439spf mb90437lpf mb90437lspf mb90438lpf mb90438lspf mb90439pf mb90439spf 100-pin plastic qfp (fpt-100p-m06) mb90f438lpmc mb90f438lspmc mb90f439pmc MB90F439SPMC mb90437lpmc mb90437lspmc mb90438lpmc mb90438lspmc mb90439pmc mb90439spmc 100-pin plastic lqfp (fpt-100p-m20)
mb90435 series ds07-13727-2e 57 package dimensions please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ (continued) 100-pin pl as tic qfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 14.00 20.00 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 3 . 3 5 mm max code (reference) p-qfp100-14 20-0.65 100-pin pl as tic qfp (fpt-100p-m06) ( fpt-100p-m06 ) c 2002 fujit s u limited f10000 8s -c-5-5 1 3 0 3 1 50 51 8 0 8 1 100 20.000.20(.7 8 7.00 8 ) 2 3 .900.40(.941.016) 14.000.20 (.551.00 8 ) 17.900.40 (.705.016) index 0.65(.026) 0. 3 20.05 (.01 3 .002) m 0.1 3 (.005) "a" 0.170.06 (.007.002) 0.10(.004) det a il s of "a" p a rt (.0 3 5.006) 0. 88 0.15 (.0 3 1.00 8 ) 0. 8 00.20 0.25(.010) 3 .00 +0. 3 5 ?0.20 +.014 ?.00 8 .11 8 (mo u nting height) 0.250.20 (.010.00 8 ) ( s t a nd off) 0~ 8 ? * * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . ?2002-200 8 fujit s u microelectronic s limited f10000 8s -c-5-6 note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder.
mb90435 series 58 ds07-13727-2e (continued) please confirm the latest package dimension by following url. http://edevice.fujitsu.com/package/en-search/ 100-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 14.0 mm 14.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm m a x weight 0.65 g code (reference) p-lfqfp100-14 14-0.50 100-pin pl as tic lqfp (fpt-100p-m20) (fpt-100p-m20) c 2005 fujit s u limited f1000 3 1 s -c-2-1 14.00 0.10(.551 .004) s q 16.00 0.20(.6 3 0 .00 8 ) s q 1 25 26 51 76 50 75 100 0.50(.020) 0.20 0.05 (.00 8 .002) m 0.0 8 (.00 3 ) 0.145 0.055 (.0057 .0022) 0.0 8 (.00 3 ) "a" index .059 ? .004 +.00 8 ? 0.10 +0.20 1.50 (mo u nting height) 0 ? ~ 8 ? (0.50(.020)) (.024 .006) 0.60 0.15 0.25(.010) 0.10 0.10 (.004 .004) det a il s of "a" p a rt ( s t a nd off) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s ?2005-200 8 fujit s u microelectronic s limited f1000 3 1 s -c-2-2 note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
mb90435 series ds07-13727-2e 59 main changes in this edition the vertical lines marked in the left side of the p age show the changes. page section change results ?? changed the package. (fpt-100p-m05 fpt-100p-m20) 47 electrical characteristics 5. a/d converter changed the item of ?zer o transition voltage? and ?full-scale transition voltage?. 56 ordering information changed the part number; mb90437lpfv mb90437lpmc mb90437lspfv mb90437lspmc mb90438lpfv mb90438lpmc mb90438lspfv mb90438lspmc mb90439pfv mb90439pmc mb90439spfv mb90439spmc mb90f438lpfv mb90f438lpmc mb90f438lspfv mb90f438lspmc mb90f439pfv mb90f439pmc mb90f439spfv MB90F439SPMC 57 package dimensions changed the figure of package. fpt-100p-m05 fpt-100p-m20
mb90435 series fujitsu microelectronics limited shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +8 1-3-5322-3347 fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. 151 lorong chuan, #05-08 new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fujitsu.com/sg/serv ices/micro/semiconductor/ fujitsu microelectronics shanghai co., ltd. rm.3102, bund center, no.222 yan an road(e), shanghai 200002, china tel: +86-21-6335-1560 fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road tsimshatsui, kowloon hong kong tel: +852-2377-0226 fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representatives before ordering. the information, such as descriptions of f unction and application circuit examples, in this document are presented solely for t he purpose of reference to show examples of operations and uses of fujitsu microelectronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to us e based on such information. wh en you develop equipment incor porat- ing the device based on such information, you must assume any responsibility arising out of su ch use of the information. fujitsu microelectronics assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of f unction and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microelectronics warrant non-i nfringement of any third-party's intellectual property right o r other right by using such information. fujitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use accompanying fata l risks or dangers that, unless extremely hi gh safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport contro l, medical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high reliab ility (i.e., submersible repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any third party for any claims or damages arisi ng in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety design measures into your facility and equi pment such as redundancy, fire protection, and prevention of ov er-current levels and other abnormal operating conditions. exportation/release of any products described in this document may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand names herein are the trademarks or registered trademarks of their respective owners. edited business & media promotion dept.

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